RealProbe
: On-FPGA profiling tool for HLS designs
Welcome to RealProbe, the on-FPGA profiling tool designed for High-Level Synthesis (HLS) designs. By simply adding #pragma HLS RealProbe
to your code, you can gain a comprehensive understanding of how your HLS designs perform on FPGA hardware, including detailed insights into all sub-modules, function calls, and loops.
Features
- Fully Automated
RealProbe is the first end-to-end profiler from HLS source code to bitstream generation and on-FPGA execution. All profiling process operates with zero user manual effort.
- Easy integration
RealProbe is fully integrated into Vitis HLS and Vivado toolchain, no extra environment settings, tool installations, or dependencies are required.
- Open source
RealProbe is publicly accessible and continuously developed and maintained for ongoing improvement and support.
Note
This project is under active development.
Attending FCCM 2024 Tutorial?
Explore our comprehensive guide to RealProbe at the FCCM 2024 tutorial:
- /tutorial/tutorial
Quick introduction to the tutorial “Understand your FPGA design better”
- /tutorial/about
Overview of what the tutorial covers.
- /tutorial/install
Step-by-step instructions to install RealProbe.
- /tutorial/usage
Guidance on how to run RealProbe in different modes.
- /tutorial/flow
Exploration of the RealProbe workflow from start to finish.
- /tutorial/ex
Dive into three hands-on examples.
Just Getting Started
We have a few places for you to get started:
- /about
What is RealProbe and why do we need it?
- /getting_started
Set up the environment to run RealProbe.
- /usage
Learn about the different running modes of RealProbe.
Aspiring RealProbe Developer?
Start with the basics of setting up your project:
- /guides/developer-guide
Learn how each RealProbe code works and the build flow of RealProbe.
- /customize
Start to modify RealProbe as a developer.
For any inquiries, please contact `Jiho Kim <https://jihoray.github.io>`_